Intel researchers see a path to trillions of transistor chips by 2030

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Intel announced that researchers envision a way to make chips 10 times denser through packaging improvements and a layer of a material just three atoms thick. And that could pave the way for putting a trillion transistors on a chip package by 2030.

Moore’s Law must be dead. Chips aren’t supposed to get much better, at least not through traditional manufacturing advances. It’s a somber performance on the 75th anniversary of the invention of the transistor. Back in 1965, Intel chairman emeritus Gordon Moore predicted that the number of components, or transistors, on a chip would double every couple of years.

That law held for decades. Chips became faster and more efficient. Chipmakers shrunk the dimensions of chips, and goodness resulted. The electrons in a miniaturized chip had shorter distances to travel. So the chip got faster. And the shorter distances meant the chip used less material, making it cheaper. And so the steady march of Moore’s Law meant that chips could become faster, cheaper and even more power efficient at the same time.

But Moore’s Law really depended on brilliant human engineers coming up with better chip designs and continuous production miniaturization. In recent years, it has become more difficult to make these advances. The chip design ran into the laws of physics. With atomic layers a few atoms thick, it was no longer possible to shrink. And so Nvidia CEO Jensen Huang recently said, “Moore’s Law is dead.”

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Intel showed how it could build chips with complex interconnect packages.

It’s not good timing, since we’re just about to start building the metaverse. Moore’s Law is critical to meeting the world’s insatiable data needs, as increasing data consumption and the drive towards increased artificial intelligence (AI) provide the greatest acceleration in demand ever.

A week after Nvidia’s CEO said so, Intel CEO Pat Gelsinger said Moore’s Law is alive and well. It’s no surprise since he has invested tens of billions of dollars in new chip manufacturing facilities in the US. Nevertheless, the researchers support him at the International Electron Devices Meeting. Intel made it clear that these advances are five to ten years out.

In papers at the research event, Intel described breakthroughs to keep Moore’s Law on track to a trillion transistors on a package in the next decade. At IEDM, Intel researchers showcase advances in 3D packaging technology with a new 10-fold improvement in density, said Paul Fischer, director and senior principal engineer of component research at Intel, in a press briefing.

“Our mission is to keep our process technology options rich and full,” he said.

These packages have been used in innovative ways in the past; Intel competitor Advanced Micro Devices announced that its latest graphics chip has a processor chip and six memory chips – all connected together in a single package. Intel said it is working with government entities, universities, industrial researchers and chip equipment companies. Intel shares the fruits of its research at places like the IEDM event.

Intel also unveiled new materials for 2D transistor scaling beyond the RibbonFET, including super-thin materials just three atoms thick. It also described new opportunities in energy efficiency and memory for higher performance computing; and advances in quantum computing.

“Seventy-five years since the invention of the transistor, innovation that drives Moore’s Law continues to meet the world’s exponentially growing demand for computing,” Gary Patton, Intel’s vice president of component research and design enablement, said in a statement. “At IEDM 2022, Intel is showcasing both forward-looking and concrete research advances needed to break through current and future barriers, deliver on this insatiable demand and keep Moore’s Law alive for years to come.”

The transistor’s 75th birthday

The layers between the chip circuits can be as little as three atoms thick.

To commemorate the 75th anniversary of the transistor, Ann Kelleher, Intel’s executive vice president and general manager of technology development, will lead a plenary session at IEDM. Kelleher will outline the ways forward for continued industry innovation – rallying the ecosystem around a systems-based strategy to meet the world’s growing demand for computing and more effectively innovate to advance at a Moore’s Law pace.

The session, “Celebrating 75 Years of the Transistor! A Look at the Evolution of Moore’s Law Innovation,” will take place at 9:45 a.m. PST on December 5.

To make the progress required, Intel has a multi-pronged approach of “growing importance and certainly a growing influence within Intel” to look across multiple disciplines.
Intel needs to move forward with chip materials, chip manufacturing equipment, design and packaging, Fischer said.

“3D packaging technology enables seamless integration of chips,” or multiple chips in a package, he said. “We’re blurring the line between where silicon ends and packaging begins.”

Continuous innovation is the cornerstone of Moore’s Law. Many of the key innovation milestones for continued power, performance, and cost improvements over the past two decades—including strained silicon, Hi-K metal gate, and FinFET—in personal computers, graphics processors, and data centers began with Intel’s Components Research Group.

Further research, including RibbonFET gate-all-around (GAA) transistors, PowerVia backside power delivery technology and package breakthroughs such as EMIB and Foveros Direct, are on the roadmap today.

At IEDM 2022, Intel’s Components Research Group said it is developing new 3D hybrid bonding packaging technology to enable seamless integration of chips; super thin 2D materials to fit more
transistors on a single chip; and new opportunities in energy efficiency and memory for higher performance computing.

How Intel will do it

Intel predicts voracious demand for computing power.

Researchers have identified new materials and processes that blur the line between packaging and silicon. Intel said it envisions moving from tens of billions of transistors on a chip today to a trillion transistors on a package, which can have many chips on it.

One way to make progress is through packaging that can achieve an additional 10 times interconnect density, leading to quasi-monolithic chips. Intel’s materials innovations have also identified practical design choices that can meet transistor scaling requirements using a new material that is only three atoms thick, allowing the company to continue scaling beyond the RibbonFET.

Intel’s latest hybrid bonding research presented at IEDM 2022 shows an additional 10x improvement in power density and performance over Intel’s IEDM 2021 research presentation.

Further hybrid bond scaling to a pitch of three nanometers achieves similar interconnect densities and bandwidths to those found on monolithic system-on-chip interconnects. A nanometer is one billionth of a meter.

Intel said it is looking at super-thin ‘2D’ materials to fit more transistors on a single chip. Intel demonstrated a gate-all-around stacked nanosheet structure using a thin 2D channel only three atoms thick, while achieving near-ideal switching of transistors on a dual-gate structure at room temperature with low leakage current.

These are two important breakthroughs needed to stack GAA transistors and move beyond the fundamental limits of silicon.

Researchers also revealed the first comprehensive analysis of electrical contact topologies of 2D materials that may further pave the way for high-performance and scalable transistor channels.

To use chip space more efficiently, Intel is redefining scaling by developing memory that can be placed vertically over transistors. In an industry first, Intel is demonstrating stacked ferroelectric capacitors that match the performance of conventional trench ferroelectric capacitors and can be used to build FeRAM on a logic die.

An industry-first device-level model captures mixed phases and defects for improved ferroelectric hafnia devices, marking significant progress for Intel in supporting industry tools to develop new memories and ferroelectric transistors.

Intel sees a path to trillions of transistor chips with multiple approaches.

By bringing the world one step closer to transitioning beyond 5G and solving the challenges of power efficiency, Intel is building a viable path to 300 millimeter GaN-on-silicon wafers. Intel’s breakthrough in this area shows a 20-fold gain over the industry standard GaN and sets an industry record for high-performance power supply.

Intel is making breakthroughs in super-energy-efficient technologies, especially non-forgetting transistors, which retain data even when the power is off. Intel researchers have already broken two of three barriers that prevent the technology from being fully viable and operational at room temperature.

Intel continues to introduce new concepts in physics with breakthroughs in delivering better qubits for quantum computing. Intel researchers are working to find better ways to store quantum information by gathering a better understanding of various interface defects that can act as environmental perturbations that affect quantum data.

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